This invention relates to level shifting circuits.
A level shifting circuit is used to shift the logic levels of a signal to higher voltages. For example, in a circuit where the logic levels are 0 volts for a xe2x80x9clowxe2x80x9d logic level and +5 volts for a xe2x80x9chighxe2x80x9d logic level, a level shifting circuit can be used so that those logic levels are 0 volts for the xe2x80x9clowxe2x80x9d logic level and +10 volts for the xe2x80x9chighxe2x80x9d logic level, in one example.
Typically, level shifting circuits are used in non-volatile memories that require the controlled and selective application of a large voltage to program, write or erase portions of the non-volatile memory, such as memory cells.
For example, in a non-volatile memory device which operates with supply voltages of 5 volts, a programming voltage of the magnitude of approximately 10 volts is typically used. For non-volatile memory devices which operate using supply voltages of 3.3 volts, a programming voltage of approximately 10 volts in magnitude is also typically used.
FIG. 1 illustrates an example of a level shifting circuit which shifts the logic levels for an input or data signal IN to higher voltage levels. The signal VNEG is a negative reference signal which can be generated by another circuit (not shown) so that VNEG goes from 0 volts to xe2x88x925 volts in order to provide a xe2x88x925 volt reference for the level shifting circuit of FIG. 1.
In overall operation and as shown in Table 1, node A and B are output nodes, wherein node A follows the value of the input or data signal IN, while node B is the complement of the input or data signal IN. When the VNEG reference signal is driven to a negative voltage level, such as xe2x88x925 volts, then an output signal can be taken across node A with respect to the VNEG signal. If the input signal IN is at a low logic level of 0 volts, then the output measured across the (A to VNEG) node is 0 volts. When the input signal IN is at a high logic level of +5 volts, the voltage at the (A to VNEG) node is +10 volts, meaning that the high logic level for the IN signal has been shifted to +10 volts.
As recognized by the present inventors, such a circuit shown in FIG. 1 is problematic in that n-channel transistors 20 and 22xe2x80x94which act as a high voltage switch to drive the output to the higher voltagesxe2x80x94may degrade over time due to the fact that the gate to source voltages across these transistors may be 10 volts when the VNEG reference signal is at xe2x88x925 volts. As the transistors 20, 22 are subjected to numerous programming voltages of, for example, 10 volts between the gate and the source of each transistor, the transistors may degrade over time. If the transistor degrades, the functionality of the integrated circuit incorporating the transistor may not perform in its expected manner, and may even possibly fail due to the degradation of the transistor subjected to the high gate to source voltage.
FIG. 2 illustrates an example of a level shifting circuit wherein p-channel transistors 24, 26 are used for the high voltage output switches. The reference voltage VPOS is generated by a circuit (not shown) which generates a voltage from +5 volts to +10 volts in order to generate an output signal measured across node (A to VPOS), or node (B to VPOS). As recognized by the present inventors, the circuit of FIG. 2 may also be subjected to degradation issues when a xe2x88x9210 volt gate to source voltage is applied to transistors 24 and 26 during level shifting operations.
As recognized by the present inventors, what is needed is a circuit for shifting the voltage levels of an input signal to higher voltage levels, while reducing the gate to source voltages on the high voltage output switching transistors. In this way, due to the reduced bias voltage applied to the gate of the high voltage switching transistors, degradation of the transistors due to the high programming voltages is reduced, thereby improving the performance of the transistors and any device in which the transistors are used.
It is against this background that various embodiments of the present invention were developed.
According to one broad aspect of one embodiment of the invention, disclosed herein is a circuit for shifting a signal from a first voltage level referenced to a first voltage reference, to a second voltage level referenced to a second voltage reference. In one embodiment, the circuit includes six switches. A first switch receives the signal; a second switch receives an inverted representation of the signal; a third switch receives the output of the first switch; a fourth switch receives the output of the second switch; a fifth switch, referenced to the second voltage reference, has an input coupled with the output of the first switch and a control coupled with the output of the fourth switch; and a sixth switch, referenced to the second voltage reference, has an input coupled with the output of the second switch and has a control coupled with the output of the third switch. In one embodiment, when the third switch and the fourth switch are on, the signal is shifted to the second voltage level measured between the input of the fifth switch and the second voltage reference. The third and fourth switches act to prevent the gate to source voltage on the fifth and sixth switches from reaching a high voltage level, such as 10 volts as shown in FIG. 1.
In one embodiment, the second voltage reference is a high voltage signal of approximately xe2x88x925 volts, and the first and second switches may be p-channel transistors; the third, fourth, fifth and sixth switches are n-channel transistors. In this embodiment, the circuit can shift an input signal at logic levels, such as 0 to +5 volts, to higher voltage levels of xe2x88x925 to +5 volts.
In another embodiment, the second voltage reference is a high voltage signal of approximately +10 volts, and the first and second switches may be n-channel transistors; the third, fourth, fifth and sixth switches are p-channel transistors. In this embodiment, the circuit can shift an input signal at logic levels of, for example, 0 to +5 volts, to higher voltage levels of 0 to +10 volts.
The circuit can further include a means for generating a control signal responsive to the level of the second voltage reference. The control signal may be coupled with the third switch and the fourth switch in order to activate the third and fourth switches when the second voltage reference has reached a particular level outside of the logic levels of the circuit (i.e., below 0 volts, or alternatively, above 5 volts).
Also disclosed herein is a method for reducing a voltage applied between a gate and a source of a transistor in a level shifting circuit. The method includes providing a first switch receiving the signal, and providing a second switch receiving an inverted representation of the signal. A first high voltage switch is provided and is referenced to the second voltage reference, and the first high voltage switch has an input coupled with the output of the first switch. A second high voltage switch is provided and referenced to the second voltage reference, the second high voltage switch has an input coupled with the output of the second switch. A third switch is coupled with the output of the first switch and with the control of the second high voltage switch, wherein the third switch responsive to the second reference voltage. A fourth switch is coupled with the output of the second switch and the control of the first high voltage switch, wherein the fourth switch responsive to the second reference voltage. In this manner, when the third switch and the fourth switch are on, the signal is shifted to the second voltage level measured between the input of the first high voltage switch and the second voltage reference, while preventing a high voltage from being applied across the gate and source of the first and second high voltage switches.
The features, utilities and advantages of the various embodiments of the invention will be apparent from the following more particular description of embodiments of the invention as illustrated in the accompanying drawings.